In most modern telecommunication networks, a community of subscribers are connected to a central office switch through a two-way distribution network, which may include one or more transmission facilities, e.g., microwave, optical, electrical, etc., and which may utilize both digital baseband and analog transmission protocols. In particular, between the central office switch and each subscriber network unit, telecommunication signals may be digitized and multiplexed for transport over relatively high bandwidth facilities, e.g., optical fiber, for greater network efficiency.
In an exemplary optical communication network, an optical line terminal ("OLT") located at a central office transmits and receives digital telecommunications data to and from a number of remotely located optical network units ("ONUs"). Data is optically transported between the OLT and the respective ONUs in the form of pulses of light. In the downstream direction, the OLT cross-connects downstream data contained in "switch" channels into "fiber" channels for optical transmission to respective ONUs. The ONUs convert the received channel light pulses into electrical signals, which are de-multiplexed and terminated on respective subscriber "line cards," which generally perform functions such as digital-to-analog conversion and power regulation, e.g., for dial tone, ringing, off-hook detection, etc., that are traditionally performed at the central office. The respective subscriber line cards are connected to individual subscriber lines, e.g., twisted wire pairs, for transport of the subscriber signals to and from respective subscriber premise locations. In the upstream direction, the OLT converts received light pulses into electrical digital data signals, and cross connects the incoming data contained in fiber channels transmitted from the respective ONUs into switch channels.
Various communication protocols may be used to support the transport of the optical signals between the OLT and the respective ONUs. For example, in an exemplary passive optical network system, the data is transmitted in successive time division multiplexed ("TDM") optical packets, or cells, wherein the data within each packet is time-division multiplexed. In order to accurately receive the incoming data packets, the OLT or respective ONU samples the incoming data signal to interpret the respective ones and zeros. This, in turn, requires that the respective OLT and ONUs be able to synchronize their sampling circuitry to the received signal, in order to correctly interpret the incoming pulses.
More particularly, in the downstream direction, a single, continuous optical data signal from the OLT is transmitted to the ONUs--i.e., wherein all ONUs receive the same downstream signal. A data sampling clock can be acquired at a respective ONU with a conventional analog clock recovery phase-locked loop circuit. However, analog clock recovery is relatively slow, with many clock cycles elapsing before the signal phase is acquired.
In particular, an analog phase-locked loop clock recovery circuit does not work well in the upstream direction, where multiple ONUs transmit differing signals on a shared upstream fiber and an accurate sampling clock at the OLT must be rapidly determined, i.e., preferably by using only a few data transitions at the beginning of each incoming packet. Further, because different signals can traverse widely varying lengths of optical fiber cable (i.e., depending on which ONU they were transmitted from), the time-of-flight transmission difference between respective ONUs results in a relative phase shift between received signals at the OLT. Coupled with the rapid frame rate used in telecommunication systems--125 microseconds per frame is standard--the phase shift between signals transmitted from multiple ONUs renders the use of a conventional analog phase-locked-loop clock recovery infeasible for the upstream receiver at the OLT. Thus, a digital phase acquisition circuit is preferred for receiving and recovering upstream data transmissions at the OLT.
Conventional digital clock recovery circuits acquire phase by means of a high-frequency clock that generates multiple phases of the clock signal. An initial phase is selected, and a control loop is run to change the data phases on an incremental basis until the optimal phase is reached. However, such clock recovery devices, while not as slow as analog clock recovery circuits, still require a relatively large number of bit times of received data before the incoming signal phase can be accurately acquired. Moreover, conventional digital clock recovery circuits are relatively expensive as they rely on high-speed digital clocks, which must be several times faster than the signal bit rate used for the clock recovery function. As the bit rate of systems increase, clock recovery circuits that rely on clocks that operate on several times the bit rate become impractical. For example, eight phases of 61 megabits per second (mbps) would require a clock speed of 488 MHz.
Thus, there is a need for a digital clock recovery device that can rapidly acquire the phase of respective incoming signals, yet can be deployed at a relatively low cost.